STM32 FMC / OCTOSPI External SDRAM & Asynchronous SRAM Timing-Register Solver

Deterministic Ceiling integer clock-period quantization N_cycles = ceil(t_ns * f_fmc_GHz) - 1 register offset + JEDEC SDRAM auto-refresh rate (T_ref_ms / N_rows)*f_clk - 20 engine (.ioc, .c, .h, .json) built for STMicroelectronics, Winbond, ISSI, Alliance Memory — zero-upload ephemeral Wasm RAM execution.