Deterministic Transmission-line signal rise-time stub limit (L_stub < t_r * v_p / 10) + Thevenin fail-safe idle bias (>200 mV) engine (.json, .svg, .pdf) built for Wiren Board, Waveshare, Eastron, Vaillant — zero-upload ephemeral Wasm RAM execution.
Running ephemeral Wasm verification…