FPGA Vivado .xdc & Quartus .sdc Source-Synchronous SDR/DDR I/O Timing Constraint Generator

Deterministic Source-synchronous / System-synchronous setup & hold inequality solver (UI/2 DDR phase window minus device skew + board trace flight-time delta) engine (.xdc, .sdc, .tcl, .json) built for AMD Xilinx, Intel Altera, Microchip PolarFire, Analog Devices — zero-upload ephemeral Wasm RAM execution.